Field of the Invention
The present invention relates to a semiconductor device and a method for manufacturing the same.
Description of the Background Art
High breakdown voltage lateral metal oxide semiconductor (MOS) transistors are described for example in the following documents:
Document 1: US Patent Application Publication No. 2012/0043608
Document 2: Japanese Patent Laying-Open No. 9-321291
Document 3: J. Sonsky, et al., “Towards universal and voltage-scalable high gate- and drain-voltage MOSFETs in CMOS”, ISPSD 2009, pp. 315-318
Document 4: A. Heringa, et al., “Novel power transistor design for a process independent high voltage option in standard CMOS”, ISPSD 2006.
Document 1 and Document 4 describe disposing a plurality of shallow trench isolations (STIs) between a gate electrode and a drain region in stripes. Document 2 describes providing between a gate electrode and a drain region a trench with an impurity containing insulating material introduced therein. Document 3 discloses a structure having an STI with a gate electrode disposed thereon.